Designing digital filter using fpga | Swiss German University Library

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Designing digital filter using fpga

Iskandar, Yoshua Pohan - Personal Name; Trihatmo, Sardjono - Personal Name;

The purpose of this thesis is to implement digital filter in an FPGA development board kit. FIR low pass filter will be implemented in this thesis. The filter will be downloaded into the FPGA, assembled with UART so that it can communicate serially to outside devices such as computer. The signal data will be generated in the computer, and will be quantized and sampled. The sampled data will be sent to the filter in the FPGA through Data terminal which will send and receive data serially. The Filtered data will then transmitted through the UART in the FPGA, accepted by the Data Terminal in the computer, and will be plotted in the computer to see the filtered result.

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B00519 (wh) Available

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Series Title: -
Call Number: 519
Publisher: : Swiss German University., 2009
Collation: -
Language: English
ISBN/ISSN: -
Classification: NONE
Content Type: -
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Edition: -
Subject(s): MT
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